Design and physical implementation of an analog receiver for a 2.5Gbps SerDes

An analog receiver module for a SerDes with a data rate of 2.5 Gbps for PCI Express Gen 1, is presented. The module is composed by a high-speed differential amplifier, a replica bias circuit and a CML to CMOS converter with duty-cycle correction. The circuit was designed in CMOS 130nm process technology with a supply voltage of 1.2V. A high gain amplifier using the self-cascode technique allows to overcome the low output impedance limitation set by the 130nm technology. Simulation results exhibit no functional issues under PVT corners and mismatch analysis, showing the circuit accomplishes the PCIe Gen 1 specification.