A Sub-50fs-Jitter Sub-Sampling PLL with a Harmonic-Enhanced 30-GHz-Fundemental Class-C VCO in 0.18 mu m SiGe BiCMOS

This paper presents a 27.0-30.5 GHz sub-sampling PLL implemented in a 0.18um SiGe BiCMOS process. The PLL incorporates an improved Class-C VCO with a supply-side 2nd-harmonic common-mode resonance and a completely floating, transformer-based PI-harmonic differential-mode resonance. Despite the limitation of the 0.18 mu m CMOS devices at high frequencies, the prototype achieves record low in-band noise of 116dBc/Hz at 100kHz offset and sub-50fs RMS jitter at 30GHz when integrated from 1kHz to 100MHz, outperforming state-of-the-art designs in advanced CMOS nodes with similar output frequencies. A single low voltage of 1.8V is used for both CMOS-and SiGe-based blocks. At 40mA, the PLL achieves an excellent jitter FoM of -247.8dB when the FLL is turned on and -250.4dB when turned off.