A 6GS/s 0.5GHz BW continuous-time 2-1-1 MASH Delta Sigma modulator with phase-boosted current-mode ELD compensation in 40nm CMOS

This paper presents a 6GS/s 0.5GHz bandwidth CT 2-1-1 MASH 3b Delta Sigma modulator in 40nm CMOS. To enable the 0.5GHz bandwidth, the modulator employs current-mode excess loop delay compensation with phase boosting, current-mode locally-time-interleaved quantizers, and on-chip comparator offset calibration to realize high-speed ELD-compensated 3-bit quantizers. High sampling frequency, multi-bit quantization and multi-stage noise-shaping enable the ADC to achieve 58dB DR in 500MHz BW when sampled at 6GHz. If sampled at 4GHz, 65dB DR can be achieved at a BW of 300MHz.