A 3.2-12.8Gb/s Duty-Cycle Compensating Quadrature Error Corrector for DRAM Interfaces, with Fast Locking and Low Power Characteristics.

Hojun Yoon, Wonjoo Jung,Jaewoo Park,Jindo Byun,Hyungmin Jin,Hyunyoon Cho,Youngmin Kim,Baekjin Lim,Young-Chul Cho,Youngdon Choi,Jung-Hwan Choi,Hyungjong Ko,Changsik Yoo,Sang-Hyun Lee

ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)（2021）

引用 6|浏览19

关键词

DRAM interface,quadrature error corrector (QEC),duty-cycle error correction (DCC),digital loop filter (DLF),successive approximation register (SAR),re-lock

AI 理解论文

溯源树

样例

生成溯源树，研究论文发展脉络

Chat Paper

正在生成论文摘要