Static Timing Analysis Induced Simulation Errors for Asynchronous Circuits

In this paper, we demonstrate that conventional Static Timing Anaysis (STA) based, functional, gate-level simulation of asynchronous circuits with cycles is only as accurate as the STA engine used. This is, firstly because cycle cuts create local slew errors at cutpoints, and secondly because slew propagation may not be upper bounded across multiple cut points in the same cycle. The use of an Asyn...