Metal Wet Recess Challenges and Solutions for beyond 7nm Fully Aligned Via Integration

B. Peethala,D. Sil,B. Briggs, D. Rath,N. Lanzillo, K. Matam,H. Shobha,K. Choi,T. Spooner,D. Canaperi,B. Haran, M. Packiam, D. Janes, J. Casey, L. Chang,K. Ryan

2021 IEEE International Interconnect Technology Conference (IITC)（2021）

Cited 2|Views33

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Abstract

The Fully aligned via scheme (FAV) is known to mitigate the via misalignment issues that drive a lower Vmax and limits the contact area between the via and the underlying line. Even though the overall benefits of FAV are well known, the key detractors and their contributions are not well understood. One of the key challenges in FAV integration is the need to create of topography which can be eithe...

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Key words

Resistance,Conferences,Metals,Surfaces,Insulators

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