A 5nm Fin-FET 2G-search/s 512-entry x 220-bit TCAM with Single Cycle Entry Update Capability for Data Center ASICs
2021 Symposium on VLSI Circuits(2021)
Abstract
This paper presents a 2G-search/s embedded Ternary Content Addressable Memory (TCAM) design in 5nm Fin-FET technology with the ability to update both SRAM words in a TCAM entry in a single clock cycle. This reduces TCAM update latency by 50% for data center Application Specific Integrated Circuits (ASICs) with only 1% area overhead and no search power penalty. We present a novel time multiplexed input bus interface on a single port TCAM cell array and new architecture to enable fast updates. Silicon measurement shows the highest reported search rate of 2G-search/s at a 3.48Mb/mm
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memory density including all global peripheral circuitry for a 512 entry, 220-bit wide, 110Kb TCAM.
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Key words
single port TCAM cell array,search rate,memory density,data center ASICs,ternary content addressable memory design,SRAM words,TCAM entry,clock cycle,area overhead,search power penalty,application specific integrated circuits,Fin-FET 2G-search,single cycle entry update,TCAM update latency,time multiplexed input bus interface,silicon measurement,global peripheral circuitry,size 5.0 nm
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