A Review of Low Temperature Process Modules Leading Up to the First (≤500 °C) Planar FDSOI CMOS Devices for 3-D Sequential Integration

C. Fenouillet-Beranger,L. Brunet,P. Batude, L. Brevard,X. Garros,M. Cassé,J. Lacord,B. Sklenard,P. Acosta-Alba,S. Kerdilès, A. Tavernier,C. Vizioz,P. Besson,R. Gassilloud, J.-M. Pedini, J. Kanyandekwe,F. Mazen, A. Magalhaes-Lucas,C. Cavalcante,D. Bosch, M. Ribotta,V. Lapras,M. Vinet,F. Andrieu,J. Arcamone

IEEE Transactions on Electron Devices（2021）

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摘要

In this article a review of low temperature (LT) (≤500 °C) process modules in view of 3-D sequential integration is presented. First, both the bottom device thermal stability and intermediate back end of line (iBEOL) versus thermal anneal and ns-laser anneal is determined, setting up the top device temperature fabrication process at 500 °C during a couple of hours. Then, the full LT process flow w...

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关键词

Annealing,Surface contamination,Field effect transistors,Semiconductor device reliability,Silicon-on-insulator,Logic gates,Very large scale integration

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