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Reference Voltage Buffer for Hybrid RC-DAC SAR ADCs in 130 Nm CMOS Process

2021 IEEE International Symposium on Circuits and Systems (ISCAS)(2021)

Cited 2|Views18
Key words
hybrid RC-DAC SAR ADC,8MSPS SAR ADC,RVB implementation,SAR ADC architectures,successive approximation register ADC,reference voltage buffer,CMOS process,current 760.0 muA,voltage 87.0 muV,size 130.0 nm,voltage 1.2 V
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