An efficient NBTI-aware wake-up strategy: Concept, design, and manipulation

Abstract High leakage power consumption has become a serious problem in modern IC design. By isolating a block of circuit which is not in use from power supply, power gating has become one of the most effective ways to reduce leakage power. During the circuit wake-up process, turning on sleep transistors simultaneously may induce excessive surge current, which will threaten signal integrity. To avoid significant surge current, sleep transistor wake-up sequence should be carefully designed. On the other hand, PMOS sleep transistors may suffer from Negative-Bias Temperature Instability (NBTI) effect, and the wake-up time is increased after circuit aging. Conventional fixed wake-up sequence-based methods do not consider the NBTI effect, which may result in longer or unacceptable wake-up time after circuit aging. Therefore, in this paper, we propose a novel reconfigurable circuit structure that can reconfigure the wake-up sequence and a novel NBTI-aware wake-up strategy to reduce the wake-up time. Our strategy first finds a set of proper wake-up sequences under different aging circumstance and then dynamically reconfigures wake-up sequences at runtime based on the actual aging scenario (i.e. different months or years of aging). Experimental results show that compared with a traditional fixed wake-up sequence approach, our strategy can reduce up to 49.78% average wake-up time latency. Meantime, according to our estimation, to implement the reconfigurable wake-up sequence structure, the parasitic area overhead is only about 0.27% with a larger benchmark.