Optimization and Implementation of a New Topology for Cascaded Multilevel Inverters with Reduced Number of Semiconductor Devices

In this paper, firstly, a new basic structure is proposed, and then, the extended structure which is made up of the series connection of the basic units is proposed. Two algorithms are presented to calculate the magnitude of DC voltage sources in order to generate all positive and negative voltage levels (even and odd) at the output. The suggested structure is optimized to generate the maximum number of output voltage levels using the minimum number of components, gate driver circuits, DC voltage sources, minimum variety of DC voltage sources and less blocking voltage on the switches. Fewer numbers of components and variety of DC voltage sources are the main advantages of the proposed topology which lead to lower cost and control complexity. The mentioned advantages are verified by comparison studies of the proposed cascaded topology with most of the other recently presented topologies. Finally, the performance of the proposed topology is confirmed by the experimental results.