3D-Split SRAM: Enabling Generational Gains in Advanced CMOS

R. Mathur,M. Bhargava, H. Perry, A. Cestero, F. Frederick, S. Hung, C. Chao,D. Smith, D. Fisher, N. Robson,X. Xu, P. Chandupatla, R. Balachandran,S. Sinha,B. Cline,J. P. Kulkarni

2021 IEEE Custom Integrated Circuits Conference (CICC)(2021)

引用 4|浏览13
暂无评分
摘要
3D integration technologies are becoming increasingly viable to mitigate the limitations and slowdown in traditional 2D transistor scaling. 3D-Split SRAMs, realized by splitting the bitlines (BL) and/or wordlines (WL) across two or more 3D-arranged tiers, promise improved power/performance due to reduced RC parasitics. However, their feasibility and efficacy depend on the pitch and RC parasitics o...
更多
查看译文
关键词
Wafer bonding,Three-dimensional displays,Conferences,Random access memory,Prototypes,Performance gain,Gain measurement
AI 理解论文
溯源树
样例
生成溯源树,研究论文发展脉络
Chat Paper
正在生成论文摘要