Design of FPGA-Implemented Reed-Solomon Erasure Code (RS-EC) Decoders With Fault Detection and Location on User Memory
IEEE Transactions on Very Large Scale Integration (VLSI) Systems(2021)
摘要
Reed–Solomon erasure codes (RS-ECs) are widely used in packet communication and storage systems to recover erasures. When the RS-EC decoder is implemented on a field-programmable gate array (FPGA) in a space platform, it will suffer single-event upsets (SEUs) that can cause failures. In this article, the reliability of an RS-EC decoder implemented on an FPGA when there are errors in the user memor...
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关键词
Decoding,Reliability,Fault detection,Matrix decomposition,Generators,Field programmable gate arrays,Logic gates
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