A Reflow-capable, Embedded 8mb STT-MRAM Macro with 9ns Read Access Time in 16nm FinFET Logic CMOS Process
2020 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM)（2020）
Key words
silicon characterization results,STT-MRAM macro,STT-MRAM film stack,solder-reflow tolerance,reverse connected reference cells,read-disturb immunity,read access time,FinFET Logic CMOS process,short write pulse,size 16.0 nm
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