Reliability on Evolutionary FinFET CMOS Technology and Beyond

During the past decades, FinFET has been the main device architecture to accelerate transistor performance. Since FinFET should be scaled down with multi-function replace metal gate (RMG) and narrow and taller fin shape, the reliability issues have been concerned as well. It is very important to address the current reliability consideration on evolutionary FinFET and would be helpful to consider the new device architecture like gate all around device beyond FinFET. The baseline reliability on gate dielectric TDDB and BTI is less impacted by work-function modulation for scaled FinFET. In order to meet the wide range of Vt, the additional dipole is utilized resulting in TDDB improvement. The self-heating effect (SHE) should be considered for the intrinsic reliability with very narrower vertical fin structure. The layout dependent self-heating characterization and its model are presented. The BEOL electro-migration needs to add the transistor level self-heating in the thermal aware EM model. Since MOL and BEOL pitch is aggressive reduced, the intrinsic reliability and extrinsic reliability should be considered at the same time. For the high-volume products, the extrinsic failures should be suppressed below ppm level. Since the physical spacing all across the critical is very close to direct tunneling regime, the TTF based reliability model should be considered with power law for FEOL, MOL and BEOL for FinFET technology and beyond.