Gate-All-Around Strained Si0.4Ge0.6 Nanosheet PMOS on Strain Relaxed Buffer for High Performance Low Power Logic Application

For the first time, we report a short channel high performance, gate-all-around strained Si _0.4 Ge _0.6 nanosheet PMOSFET with aggressively scaled dimensions. We demonstrate realization of s-Si _0.4 Ge _0.6 nanosheet with 5nm thickness and device with L _G =25nm featuring record high I _ON =508 μA/μm at I _OFF =100nA/μm and V _DS = -0.5V. This result is obtained with the combination of (a) novel Si-cap-free gate oxide solution featuring thin EOT=9.1A, low D _IT and N _IT for s-Si _0.4 Ge _0.6 channel, (b) record high hole mobility= 450 cm ² /Vs owing to compressive strain imparted by Si _0.7 Ge _0.3 strain relaxed buffer (SRB), (c) low R _EXT =150 Ω-μm due to highly active, strained source/drain SiGe process and novel p++ cap layer, (d) optimized source/drain tip and junction to minimize GIDL impact to I _OFF . Additionally, the impact of operating temperature on GIDL and I _OFF is comprehensively studied to prescribe optimal V _CC range of operation for this technology.