A low-power high-resolution dynamic voltage comparator with input signal dependent power down technique

A high-resolution dynamic voltage comparator with an input signal dependent power down technique for low power applications is presented here. Without affecting the resolution, a preamplifier stage has been removed from the proposed dynamic voltage comparator in order to reduce the power consumption and its delay. In this design, an input signal dependent power-down technique is used. The proposed design consists of NMOS & PMOS Input Stage Dynamic Voltage Comparator with power down (NISDVC_PD & PISDVC_PD) along with multiplexers for full rail-to-rail input swing. One out of PISDVC_PD and NISDVC_PD is active at a time to reduce power consumption. The proposed comparator has been designed using SCL 180 nm CMOS technology at 1.8 V. The simulation results of the proposed design show that the power consumption and delay is 94.1 µW and 208.28 ps at 500 MHz whereas at 2 GHz the value of the power consumption and delay is 147.7 µW and 212.5 ps, respectively. Furthermore, the offset voltage is obtained as 185.3 µV and the sensitivity of the circuit is 0.15 µV.