A Theoretical Framework For Trap Generation And Passivation In Nand Flash Tunnel Oxide During Distributed Cycling And Retention Bake

MEmory Reliability Investigation Tool (MERIT) framework, with a generic Reaction-Diffusion-Drift (RDD) model is used to simulate the channel interface (Delta N-rr) and bulk oxide (Delta N-OT) traps time kinetics in the tunnel oxide (TO) of NAND Flash during Erase-Program (EP) cycling and retention bake after cycling. The generation and passivation of traps are calculated from cycle-to-cycle during distributed EP cycling, and trap passivation is calculated during bake. The framework can model multiple EP cycling phases with varying EP cycling delays, and EP cycling and bake temperature (T). The use of different EP cycling T to mimic the distributed cycling impact is analyzed. The Universal Detrapping Metric (UDM) for various inserted delays and cycling temperatures is verified.