A 25Gb/s 185mW PAM-4 Receiver with 4-tap Adaptive DFE and Sampling Clock Optimization in 55nm CMOS

Liangxiao Tang,Weixin Gai,Chih-Kong Ken Yang,Bingyi Ye,Congcong Chen

2021 IEEE International Symposium on Circuits and Systems (ISCAS)（2021）

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摘要

A 25Gb/s PAM-4 receiver is presented with 4-tap adaptive DFE and sampling clock optimization. PAM-4 signaling suffers more from non-optimal sampling clock phase which degrades BER. By finding the point with the least pre-cursor ISI, the sampling clock can be recovered with optimal phase, which improves the BER by as much as 109 through 12.5dB channel loss. A novel clocked amplifier is implemented ...

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关键词

Power supplies,Circuits and systems,Receivers,CMOS technology,Delays,Optimization,Clocks

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