Gate Delay Estimation With Library Compatible Current Source Models and Effective Capacitance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems(2021)
摘要
As process geometries shrink below 45 nm, accurate and efficient gate-level timing analysis becomes even more challenging. Modern VLSI interconnects are more resistive, signals no longer resemble saturated ramps, and gate input pins exhibit a significant Miller effect. Over recent years, the semiconductor industry has adopted current source models (CSMs) for accurate gate modeling. Industrial gate...
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关键词
Logic gates,Load modeling,Computational modeling,Capacitance,Libraries,Delay estimation,Integrated circuit interconnections
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