P-FMA: A Novel Parameterized Posit Fused Multiply-Accumulate Arithmetic Processor

Sandra Jean,Aneesh Raveendran,A. David Selvakumar, Gagandeep Kaur,Shankar G Dharani,Shashikala Gunderao Pattanshetty,Vivian Desalphine

2021 34th International Conference on VLSI Design and 2021 20th International Conference on Embedded Systems (VLSID)（2021）

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摘要

IEEE 754–2008 based Floating Point Unit (FPU) is computationally complex and consumes higher resources depending on precision and dynamic range viz. half/ single/double/quad precision. In order to optimize and balance the resources with Accuracy Vs Precision Vs Dynamic range, researchers had recommended and adopted trans-precision arithmetic or approximate arithmetic. Posit data type is an alterna...

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关键词

Microarchitecture,Embedded systems,Heuristic algorithms,Dynamic range,Very large scale integration,Approximation algorithms,Kernel

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