PositGen-A Verification Suite for Posit Arithmetic

Typically verification of arithmetic units is based on simulation/emulation with random / coverage models enabled constrained test vectors or formal techniques. Our PositGen generates coverage models based Posit domain vectors, enabling a native PositIn and PositOut verification paradigm for Posit units covering corner and special cases. It generates vectors for Add, Sub, Mul, Fused Multiply Add/S...