Cost-effectively improving solid state drive lifetime by hierarchical redundancy and heterogeneous memories

Solid state drives (SSDs) built upon MLC NAND flash memories suffer from a low lifetime endurance induced by continuously scaling-down feature sizes and increasing bit density per cell. To cost-effectively address this problem, we propose to integrate both hierarchical data redundancy and heterogeneous flash memory techniques into the SSD, named H2-SSD. Through deploying across-chips data redundancy in addition to conventional in-page error correction codes, error correction capacity, so does the lifetime endurance of H2-SSD can be dramatically improved. Furthermore, an extra small-size sisngle-level cell (SLC) chip is integrated into H2-SSD to store across-chips parities. Due to the high program/erase performance and lifetime endurance of that SLC chip, I/O performance degradation induced by the hierarchical data redundancy can be significantly mitigated, even under strict synchronous parity update strategies. Quantitative analysis and trace-driven simulations are conducted to evaluate the effectiveness and efficiency of H2-SSD, in both the scenes with and without degraded reads. Experimental results demonstrate that H2-SSD outperform the conventional SSD in maximum Program/Erase cycles by 23% to 178%, and suffer from negligible degradation of I/O performance in terms of both throughput and average response time in most cases.