Area Efficient High Speed Multi Operand Adder using 22nm Strained Silicon CMOS Technology

In this proposal work, the ripple carry adder (RCA)based binary tree adder (BTA) is analysed to find the possibilities for area minimization. Based on the analysis, critical path of carry is taken into the new logic implementation and the corresponding design of RCA are proposed for the BTA. The RCA is designed for m bits (m=8,16,32 bits) offers better efficiency in terms of area, delay than the existing RCA. Using this RCA design, the multioperand adder (n=8,16,32) BTA structure is proposed. The synthesis is done at 22nm Cmos technology. Result reveals that the proposed BTA-MOA provides the efficient results in area minimization and also delay efficient structure for multipliers and other applications. Therefore, this binary tree adder based multioperand design can be a better choice to develop the efficient digital systems for signal and image processing applications.