INTERVAL SIMULATION WITH CYCLE LEVEL MEMORY HIERARCHY SUPPORT

A method and system are described for simulating a set of instructions to be executed on a processor. The method comprises using an analytical model comprising a timing estimator and estimating timing information of the processor. Estimating timing information thereby comprises issuing memory accesses in the same way as an actual out-of-order processor would issue them or taking into account if instructions incur a long-latency access miss event for which a penalty is taken into account and the occurrence of a long latency access miss event is determined in a dynamic way.