A 3nm Gate-All-Around Sram Featuring An Adaptive Dual-Bl And An Adaptive Cell-Power Assist Circuit

Advanced technologies help to improve SRAM performance via recent transistor breakthroughs [1], which allow SRAM designers to focus on handling metal resistance by alleviating device performance impediments. Since SRAM margins are more vulnerable to the increasing metal resistance, due to smaller critical dimensions, SRAM-assist circuits are proposed to overcome the impact of metal resistance in recent technologies [2 –5]. One of the challenges is the design limitation such as the quantized transistor, which requires SRAM-assist to optimize SRAM margins. In this paper, gate-all-around (GAA) SRAM design techniques are proposed, which improve SRAM margins more freely, in addition to power, performance, and area (PPA). Moreover, SRAM-assist schemes are proposed to overcome metal resistance, which maximizes the benefit of GAA devices.