Optimization Design And Fpga Implementation Of Orthogonal Matching Pursuit Algorithm

In reconstruction algorithm of Compressed Sensing, it needs to gather more Information sample points for real-time signal streams whose sparsity is larger. But it is extremely difficult to implement the high-dimensional matrix multiplication on hardware. This paper presented a novel hardware architecture for Orthogonal Matching Pursuit (OMP) algorithm. OMP algorithm was improved to reduce the number of multiplications. Alternative Cholesky Decomposition (ACD) which avoids square root calculations was used in the part of matrix decomposition to decrease computation delay. The parallel implementation and resource multiplexing were utilized to improve computing speed and resource utilization. This design was described by using RTL HDL, implemented with Altera's PFGA Cyclone II EP2C70F672C6. The timing simulation was carried under the Quartus II. Simulation results verify the correctness of the design.