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基于0.13μm CMOS工艺的14位50MS/s流水线ADC

Yong ZHAN,Hong SHI,Juan WEI,Xiaodan ZHOU,Liang GUO

Microelectronics（2018）

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Abstract
设计并实现了一种14位50 MS/s流水线ADC.采用无采保放大器的前端电路和运放共享技术,在达到速度及精度要求的同时降低了功耗.该流水线ADC采用0.13tm标准CMOS工艺实现,芯片尺寸为2.7 mm×2.1 mm.在电源电压为1.2V、采样速率为50 MS/s、模拟输入信号频率为28 MHz的条件下进行测试.结果表明,该ADC的功耗为91.2 mW,SFDR为82.39dBFS,SNR为72.45 dBFS,SNDR为71.13 dB,ENOB为11.52 bit,THD为-81.28 dBc,DNL在±1 LSB以内,INL在±3 LSB以内,品质因子FOM为0.62 pJ/step.
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