一种缓冲器阻抗动态调整的LDO
Microelectronics(2017)
Abstract
提出了一种缓冲器阻抗动态调整的LDO结构.采用并联负反馈和阻抗动态调整技术,显著降低了缓冲级的输出阻抗,没有增加额外的静态电流,功率管栅极极点始终远在单位增益带宽之外,对稳定性没有影响.该缓冲级增大了功率管栅极的摆率,提高了LDO瞬态响应性能.基于TSMC 0.18 μm 3.3 V CMOS工艺进行设计,该LDO的输出电压为1.8V,压差电压为0.2V,最大输出电流为100 mA.仿真结果显示,LDO的静态电流只有5μA,当负载电流在10 ns内从0mA跳变到100 mA时,输出欠冲和过冲电压分别为88.2mV和34.8 mV.
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