FPGA Realization of the Reconfigurable Mesh Counting Algorithm

Pass transistor logic (PTL) is a circuit design technique wherein transistors are used as switches. The reconfigurable mesh (RM) is a model that exploits the power of PTLs signal switching, by enabling flexible bus connections in a grid of processing elements containing switches. RM algorithms have theoretical results proving that switching+signal-broadcasting can speed up computations significantly. However, the RM assumes that the latency of broadcasting a signal through n switches (bus length) is 1. This is an unrealistic assumption preventing physical realizations of the RM. We propose the restricted-RM (RRM) wherein the bus lengths are restricted to k=n1d, d=2,3, horizontal ellipsis . We show that counting the number of 1-bits in an input of n bits can be done in 2d steps for d=2,3, horizontal ellipsis by an nxn RRM. An almost matching lower bound is presented, using a technique which adds to the few existing lower-bound techniques in this area. Finally, the algorithm was directly coded over an FPGA, outperforming an optimal tree of adders. This work presents an alternative way of counting, which is fundamental for summing, beating regular Boolean circuits for large numbers, where summing a vast amount of numbers is the basis of any accelerator in embedded systems such as neural-nets and streaming.(a)