An extensive survey on future direction for the reduction of noise coupling problem in TSV based 3-dimensional IC integration

Over the period of meticulous scaling IC's are crucially waiting for a platform which is planar. The most important and actual restriction is nothing, but delay of interconnect is almost approximate to that of devices. To achieve the demands of system performance, new interconnecting materials along with experimental architectures need to be developed. A new integration approach is developed which is nothing but 3D integration technology because this technology is most advantageous and famously used in comparisons to other technologies. Also 3-D technology has a capacity to ensemble with CMOS application because it can easily connect many devices in layers and can be stacked vertically with interconnecting wires having higher thickness among the layers. In this TSV's plays an important job, which can enable 3-D IC platform. Noise coupling from TSV-to-TSV and TSV-to-Substrate is estimated inside the heterogeneous integration. A vertical TSV pattern is developed to decrease the area per TSV, capacitive coupling and make constructive inductance compared to other design patterns. By developing the vertical TSV patterns in 3D IC the functionality became easier with lesser TSV's. (C) 2020 Elsevier Ltd. All rights reserved.