A Weak Asynchronous RESet (ARES) PUF Using Start-up Characteristics of Null Conventional Logic Gates

Physical unclonable functions (PUFs) are widely researched security primitive in the digital and analog domain but have yet to be explored for asynchronous circuits. In this paper, we propose novel optimization methods to design a weak Asynchronous RESet (ARES) PUF that exploits random start-up characteristics of Threshold M of N Null Conventional Logic (NCL) gates as a source of entropy. We employ two different methods to design the ARES PUF. The first includes traditional delay matching techniques using linear programming-based optimization, whereas the second one uses the genetic algorithm (GA) with delay matching as a fitness function. Both methodologies are explained with analysis and design specifications required to model NCL TH22 gates to achieve PUF characteristics. Threshold 2 of 2 (TH22) and 4 of 4 (TH44) gates are used as test cases for evaluation and comparison. Simulation results using initial delay matching techniques at 90nm and 65nm technology in HSPICE shows that the proposed ARES PUF has a uniqueness of 49.98% and reliability of 96.53% across VDD variation (±10%) and 93.39% across temperature variation (0°C-80°C). Whereas, the GA method can optimize NCL cells to form a PUF with 49% uniqueness at 65nm with an average reliability of 96.4% across VDD and 93.82% across temperature. Preliminary silicon results for proposed TH22 at TSMC 90nm technology node shows a 34% improvement in uniqueness compared to standard TH22 gate with best-case uniqueness of 53.3% and reliability of 100% respectively across repeated measurements (noise). Unlike standard TH22, standard TH44 performs better with 47.62% best-case uniqueness and 98.1% reliability ¹ .