A 10-bit 200MS/s SAR ADC with reference buffer in 40nm CMOS

Jingfu Chen,Xinpeng Xing,Zhanpeng Yang,Haigang Feng,Zhihua Wang

2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)（2020）

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摘要

A 10-bit 200MS/s SAR ADC with reference buffer is presented in this paper. Segmented capacitive DAC with MSB split-capacitor switching sequence is introduced to reduce chip area and power dissipation. Bit redundancy is applied in the ADC to relax requirement on the integrated buffer. The simulation results in 40nm GP CMOS show that the ADC achieves 60.8 dB SNDR and 71.6 dB SFDR under 200 MS/s sampling rate and Nyquist input frequency. The core SAR ADC consumes only 1.40mW power consumption and achieves a FoM of 7.8 fJ/step.

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关键词

reference buffer,segmented capacitive DAC,MSB split-capacitor switching sequence,bit redundancy,integrated buffer,core SAR ADC,power consumption,power 1.4 mW,size 40.0 nm

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