An Efficient Dadda Multiplier using Approximate Adder

In most multimedia applications, human beings can gather useful information from approximate outputs. The approximation concept is dominating in the field of digital signal processing and multimedia applications as it allows the reduction of area and power significantly with some loss of accuracy. Little inaccuracy does not affect the visual quality as it seems unnoticeable in the perception of a human eye. As an advantage, this technique is to reduce the device utilization for such applications, which will eventually lead to a reduction in terms of power as well as transmission speed. Finally, the redundant bit, as well as the storage required to store the data, will be reduced. The approximation of arithmetic circuits is useful for reducing its computational complexity without a significant impact on its coding performance. In the end, the proposed approximate almost full adder based dada multiplier utilizes less power, delay, and device utilization. In this paper, analysis of various multipliers using approximate almost full adder is evaluated.