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All-Digital Calibration Technology Based on Sign Judgment for TIADC Timing Mismatch

2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)(2020)

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摘要
This brief proposes an efficient all-digital calibration technique suppressing the timing mismatch effect in time-interleaved analog-to-digital converters (TIADCs). The timing mismatch is estimated based on a sign judgment strategy which is realized by detecting the sign of correlations difference between adjacent channels of TI-ADC, and is compensated by an high-accuracy high-order cascade Taylor algorithm. Compared with traditional techniques, it does not require any reference channels or adaptive digital filters, and can achieve an effective calibration in the whole Nyquist frequency range. Applied in a 12-bit 400MS/s four-channel TIADC, FPGA experiment results show that, with calibration, the signal-to-noise plus distortion ratio (SNDR) raises from 30 dB to 73 dB and the peak INL is reduced from 9 least significant bits (LSB) to 0.6 LSB with a normalized frequency of single-tone input signal f in /f S =0.45.
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关键词
signal-to-noise plus distortion ratio,least significant bit,FPGA,reference channel,TI-ADC adjacent channel,TI-ADC timing mismatch,all-digital calibration technology,Nyquist frequency range,adaptive digital filters,high-accuracy high-order cascade Taylor algorithm,time-interleaved analog-to-digital converters,timing mismatch effect
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