An Efficient PWL Memristor Model Towards Circuit Design

Memristor model is a kind of necessities in the design of memristive chips. Though numerous memristor models exist, they are usually too complicated to exhibit satisfactory simulation speed in large scale arrays. In this paper, we propose a piecewise linear model which has extraordinary simulation efficiency. The model parameters can be adjusted to fit TiN/TaOx/HfOx/TiN memristors. The model is described by continuous state equations which contains only multiplication and addition thus the computation and memory consumption in large scale array simulation is significantly reduced. Simulation on memristor network shows that our model reduces simulation time by at least 5% than state of the art models.