RC Tightened Corner Test structure Design and Silicon Characterization in FinFET Technology

In this work, we propose a novel RC tightened corner test structure for FinFET Technology. In this test structure, Parasitic RC DUTs (Design Under Test) integrated into RO (Ring Oscillator) have been designed to verify and calibrate MEOL (Mid-End-Of-Line) and BEOL (Back-End-Of-Line) RC tightened corner; On the other hands, addressable-array circuit has been used to avoid noise induced by the local variation of FEOL (Front-End-Of-Line) transistors. By the test structure silicon data, RC tightened corners generated from statistical simulation have been iterated and updated