Implementation and Analysis of a memory-semantic interconnect based on Gen-Z Protocol

Industrial standard activities of memory expansion protocol are emerging due to the restriction of memory bandwidth per CPU core. In this paper, we implement a memory-semantic interconnect with FPGAs based on Gen-Z protocol which is an open memory-semantic protocol. The implemented memory-semantic interconnect supports byte-addressable memory access and block memory access simultaneously. The performance of the memory-semantic interconnect is measured and analyzed in terms of latency and bandwidth by using benchmark programs. The results show that a request that utilizes the Gen-Z protocol has a few benefits compared to SSD and local memory when data size is small. We also suggest how the performance can be improved on software and hardware on both sides.