A Device For Paired Zeroing Of Numbers In A Residue System

The paper studies the problem of developing a high-speed number correction device in computing systems operating in the basis of non-positional arithmetic in residual classes. The topicality of the problem is necessitated by the search of solutions allowing reducing the time for digital processing of signals in non-positional neuroprocessors. The device allows correcting errors with single and multiple control bases of the residue system. The work presents the structure of the unit that realizes the paired zeroing on numbers in the system of residual classes. It was demonstrated that the suggested solutions allow appreciably reducing the time consumption by digital processing of signals in neuroprocessors destined for operations of summation and multiplication.