Novel Method for Verification and Performance Evaluation of a Non-Blocking Level-1 Instruction Cache designed for Out-of-Order RISC-V Superscaler Processor on FPGA

Performance of instruction cache has become an important factor in enhancing the overall performance of a system. This paper describes a novel method to evaluate the performance of a level-1 instruction (L1i) cache designed for single-core, out-of-order (OoO) RISC-V superscalar processor. A synthesizable high-level Bluespec System-Verilog (BSV) based framework, consisting of front-end model of an O<;span style="font-size: 14.5px;">o<;/span>O superscalar RISC-V processor, TLB model and lower-level memory, is used to evaluate a virtually-indexed-physically-tagged (VIPT), nonblocking, pipelined, wide fetch-group L1i-cache. The framework works in various modes, depending on the bandwidth and latency across various interfaces of processor, TLB, L1i-cache and lower-level memory. It allows variation in terms of variable latency of lower-level of memory and variable demand for instructions, simulating varying processor execution rates. The performance of the cache was evaluated through parameters such as hit-rate, MPKI, bus-traffic and hardware complexity. The objective of the paper was to evaluate and analyze different cache optimizations, viz. cache replacement policies, victim-cache buffer size/replacement policies and prefetch-unit enablement, on a baseline L1i-cache configuration. The analysis yielded in an effective L1i-cache configuration after running standard workload programs and benchmarks in single-core environment. The framework and L1i-cache were validated on Xilinx UltraScale+ VCU118 board.