Classification based scheduling in Heterogeneous ISA Architectures

Heterogeneous-ISA multi-core architectures are emerging as promising architectures to enhance single-threaded performance. Multiple cores in such architectures differ in their Instruction Set Architectures (ISAs). To achieve maximum performance gain, the program needs to be divided into several phases and each phase should run on its best affine core. Hence, the best affined core for each phase is needed to be known dynamically apriori. In this work, we propose a classification based technique that attempts to classify the phase of the program into the class of core (in terms of microarchitecture and ISA) it is most suited to. This technique leverages several online hardware performance counters to accurately predict the most affine core for each phase. Results show that our classification based predictor achieves single thread performance average speedup of 35.7% with respect to a baseline single ISA heterogeneous architecture.