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Formal Verification of Completion-Completeness for NCL Circuits

Son N. Le,Sudarshan K. Srinivasan,Scott C. Smith

2020 IEEE 63RD INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS)（2020）

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Abstract
Ensuring completion-completeness is required for delay-insensitivity when utilizing bit-wise completion to pipeline NCL circuits comprised of input-incomplete logic functions. Hence, this work presents an automated formal method to detect NCL circuits that are not completion-complete.
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Key words
asynchronous circuits,formal verification,formal methods,equivalence checking,NULL Convention Logic
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