A 170 mu W Image Signal Processor Enabling Hierarchical Image Recognition for Intelligence at the Edge

Hyochan An,Siddharth Venkatesan,Sam Schiferl,Tim Wesley,Qirui Zhang,Jingcheng Wang,Kyojin Choo, Shiyu Liu,Bowen Liu,Ziyun Li,Hengfei Zhong,Luyao Gong,David Blaauw,Ronald Dreslinski,Dennis Sylvester,Hun Seok Kim

2020 IEEE Symposium on VLSI Circuits（2020）

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摘要

We propose an ultra-low power (ULP) Image Signal Processor (ISP) that performs on-the-fly in-processing frame (de)compression and hierarchical event recognition to exploit the temporal and spatial sparsity in an image sequence to achieve a 16x imaging system energy gain. The ISP is fabricated in 40nm CMOS and consumes only 170 mu W at 5 fps for neural network-based intruder detection and 192x compressed image recording.

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关键词

ISP,hierarchical event recognition,image sequence,compressed image recording,imaging system energy gain,hierarchical image recognition,ultra-low power image signal processor,CMOS,size 40.0 nm

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