High speed VLSI architecture for improved region based active contour segmentation technique

Active contour segmentation is an important stage in image analysis applications. In this article, an improved region based active contour segmentation is proposed. The proposed active contour model speeds up the contour convergence by up to 40% while maintaining the advantages of a local region based active contour model by reducing the number of iterations. Moreover, we propose a low-complexity pipelined VLSI architecture for improved region based active contour model targeting FPGA and 90 nm ASIC platforms. The proposed pipelined design offers an increased speed of operation. Its complexity is independent of the size of image.