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Buried Power Rail Integration with FinFETs for Ultimate CMOS Scaling

Anshul Gupta,Olalla Varela Pedreira,Goutham Arutchelvan,Houman Zahedmanesh,Katia Devriendt,Hans Mertens,Zheng Tao,Romain Ritzenthaler, Shouhua Wang,Dunja Radisic,Karine Kenis,Lieve Teugels,Farid Sebai,Christophe Lorant,Nicolas Jourdan,Boon Teik Chan,Sujith Subramanian,Filip Schleicher,Toby Hopf,Antony Premkumar Peter,Nouredine Rassoul,Haroen Debruyn, Ingrid Demonie,Yong Kong Siew,Thomas Chiarella,Basoene Briggs,Xiuju Zhou,Erik Rosseel,An De Keersgieter,Elena Capogreco,Eugenio Dentoni Litta,Guillaume Boccardi,Sylvain Baudot,Geert Mannaert, Noemie Bontemps,A. Sepulveda,Sofie Mertens,Min-Soo Kim,Emmanuel Dupuy,Kevin Vandersmissen,Sara Paolillo,Dmitry Yakimets,Bilal Chehab,Paola Favia,Christel Drijbooms, Joris Cousserier,Manoj Jaysankar,Frederic Lazzarino,Pierre Morin,Efrain Altamirano,Jerome Mitard,Christopher J. Wilson,Frank Holsteyns,Juergen Boemmels,Steven Demuynck,Zsolt Tokei,Naoto Horiguchi

IEEE TRANSACTIONS ON ELECTRON DEVICES（2020）

Cited 26|Views73
Key words
3 nm,back-side power distribution network (BS-PDN),buried power rail (BPR),CMOS area scaling,Moore's law,N3,scaling booster
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