Complementary FET Device and Circuit Level Evaluation Using Fin-Based and Sheet-Based Configurations Targeting 3nm Node and Beyond

Complementary FET (CFET), implemented by stacking NMOS and PMOS on top of each other, is considered as an emerging option to continue logic scaling beyond 3nm node. It can be configured with a fin-on-fin (fin-based CFET) or sheet-on-sheet (sheet-based CFET) structures. In this paper, we use 3D-TCAD simulation to compare those two configurations at both device and circuit levels. For accurate comparison between these two CFET configurations, we deploy a drift-diffusion simulation framework, calibrated to semi-classical sub-band BTE (Boltzmann Transport Equation). We show that for the same effective channel width, nMOS of sheet-based CFET has 10% higher drive-current compared to fin-based CFET. For pMOS, sheet-based CFET shows 5% lower drive-current compared to fin-based CFET. When compared for the same device footprint with increased nanosheet width, nMOS and pMOS sheet-based CFET shows 73% and 47% higher drive current respectively compared to fin-based CFET. Using 31-stage ring-oscillator as a representative circuit, we show that for the same electrical channel width, the circuit performance of the sheet-based CFET is 2.6% higher than the fin-based CFET at Vdd of 0.7V. When compared for the same device footprint, sheet-based CFET shows 9% higher circuit performance compared to the fin-based CFET.