A 0.21V 40nm NAND-ROM for IoT Sensing Systems with Long Standby Periods

IoT sensing systems usually have long standby periods to lengthen the battery lifetime. Low active and standby power consumption is an indispensable design goal for devices, such as the read-only memory (ROM) for code storage, used in these systems. Sub-threshold (sub-Vt) designs can help accomplish the goal. A 90nm NAND-ROM achieved a state-of-the-art minimum supply voltage (Vmin) of 0.25V by using a source-line control scheme to reduce the impact of leakage and noise and using a code-inversion-based flag-table (CIB-FT) and a data-aware sensing reference (DASR) scheme for performance improvement. For advanced IoT sensing systems designed in a more advanced CMOS process with a more aggressive Vmin, more considerable leakage and higher PVT variations become the main design challenges of the sub-Vt ROM. In this paper, we first illustrate the design challenges and considerations to reach the goal of a Vmin of no higher than 0.25V for the state-of-the-art ROM redesigned in 40nm CMOS. We then propose new design techniques, including flag-table-free architecture and the new bit-line load and sense amplifier for meeting the higher stringent design specifications. Comparison results according to post-layout simulations show that the proposed 40nm ROM achieve a 17%, 16%, 43%, and 91% reduction in area, Vmin, active power, and standby leakage power, respectively, compared to the redesigned NAND-ROM.