Ultra-Low Voltage 4-to-2 Compressors for Near-Vth Computing

This paper presents two novel circuit arrangements for an ultra -low voltage, low -power 4 -to-2 compressor targeting typical near-Vh application domain. A hybrid logic style is utilized to exploit energy efficiency by means of parasitic reduction in circuit blocks. Proposed structures are evaluated against prevalent compressors in terms of their typical figure of merits and noise immunity. From extensive post-layout simulations in 65-nm bulk CMOS process technology, the most optimal arrangement was found to be 35% more power efficient, 3.4% faster, 8% more area efficient and 37% better in PDP at 0.4Voo compared to most appealing implementations in literature.