Epitaxial SiGe seed layer thickness for PFET performance tuning

SiGe alloys have been widely used as stressors in source/drain (S/D) regions for advanced complementary metal-oxide-semiconductor (CMOS) technologies to enhance channel mobility and boost device performance. Many previous studies were mainly focused on investigation of the main epitaxial SiGe layer’s growth mechanism, and its impact on the downstream process and device performance. In this work, instead of focusing on the main epitaxial SiGe layer, we present a method for tuning the device performance through adjustment of the epitaxial SiGe seed layer growth time/thickness. Experiments on patterned wafers show that the SiGe seed layer thickness has a strong impact on device performance while not affecting the subsequent epitaxial growth of SiGe S/D. This demonstrates that SiGe seed layer thickness can be a promising knob for tuning the device performance.