Self-Healing Design In Deep Scaled CMOS Technologies (Invited Paper)

Deep scaled CMOS technologies are losing their glamour because of their sensitivity to process, supply voltage, and temperature (PVT) variations. Largely because of the marginality issue, analog and mixed-signal circuits have failed to effectively exploit the high-speed and low-noise properties that deep scaled CMOS technologies provide. Large variations in leakage current and threshold voltage also make highly integrated digital designs challenging. Consequently, there is an increasing need for a new design technique that can provide high yield and reliability under large PVT variations. Among several post-silicon calibration and repair strategies proposed to address the PVT variation issues, self-healing technique based on real-time sensing and built-in feedback has received great attention because of its inherent advantage of dynamic adaptation to temporal parameter variations. This paper discusses how self-healing techniques can be used for increasing marginalities in deep scaled CMOS technologies, and also examines the remaining issues and challenges.